Integrated circuits (“ICs”) are incorporated into many electronic devices and the design process for a new IC includes several steps by using, for example, automated electronic design automation (“EDA”) tools. The design process can include (1) determining an initial design of the IC; (2) generation of a layout of the design; and (3) verification of the design. During the initial design, a user (of the EDA tool) or designer can identify a set of functions to include in the design, along with their standard delays. The user can also use computer implemented tools to perform functional simulation to ensure that the design performs a pre-simulation. If the design meets circuit performance requirements in the pre-simulation, the user can then initiate floorplan and layout phases to generate an actual layout. For example, the user can generate at least one GDS file that includes the layout of the IC.
Following the layout process, the user can verify the design by using the EDA tools to perform design rule checks (“DRC”), layout versus schematic (“LVS”) checks, and RC extraction. In cooperating with RC technology file, the RC extraction tool takes into account the layout of the conductive (e.g., metal) lines of the interconnecting layers generated by the router and computes parasitic resistance and capacitance elements associated with each conductive line. Then a post-simulation verifies circuit performance. The accuracy of post-simulation requires an accurate RC technology file.
In at least some known RC technology file accuracy tuning processes, the user can conduct accuracy tuning of the 2.5 dimensional RC technology file. In at least some known RC techfile tuning methods, the user may tune-up the input profile used for RC technology file generation. For example, the user may change actual parameters, such as the vertical height, width, or dielectric constant of the newly designed IC and/or of the components therein. However, such a method is very time consuming for application programming interface (API) RC techfile generation flow because a three dimensional characterization on every tuned-up profile can take up to approximately one day for each change. Moreover, tuning of a three dimensional profile of, for example, a Fin field effect transistor (“FinFET”), can be complex because of the number of parameters involved. Further, such a method can be difficult to model or take into account silicon effects.